CoachThe memory ordering of an atomic operation states what other memory accesses it orders. In acquire–release ordering, a load with acquire that reads the value written by a store with release sees every write the storing thread made before that store: the pair publishes data. Sequential consistency, the default of C++ atomics, adds a single total order of all such operations that every thread agrees on, as if they were interleaved on one processor. A relaxed operation is atomic but orders nothing else.
x = 1; r1 = y, thread B runs y = 1; r2 = x, a million times each. Under sequential consistency at least one read sees 1; with weaker orderings, the stores still in each core’s store buffer let both read 0, rarely but really. Measured on a laptop (Intel Core Ultra 7 155H) under WSL2, no isolated cores. Data: bench_lockfree.py.