¿Qué es Register-transfer level, hardware description language?

A design written at register-transfer level (RTL) describes, for every clock cycle, how the values held in registers are computed from the registers’ previous values and the inputs, through combinational logic. A hardware description language (Verilog, SystemVerilog, VHDL) is a language in which such designs are written: its statements describe circuits that all operate at once, not instructions executed in order.