المدربA testbench is the code that drives a design’s inputs in simulation and checks its outputs. A cycle-accurate model is a software model of a design that reproduces its outputs cycle by cycle, used as a reference against which the hardware is checked, and as a fast stand-in for it.
| Cycle | Input accepted | Outputs registered at the end of the cycle |
|---|---|---|
| 0 | beat 0: bytes 10–17 | — |
| 1 | beat 1: bytes 18–1f, last | — |
| 2 | — | field 16171819; CRC-32 f4a7fd67 |
| 3 | — | comparison (one stage): at most the threshold |
| 4 | — | comparison (two stages): at most the threshold |
hdk_top in Verilator, no back-pressure: a 16-byte frame of bytes 10 to 1f, the field at bytes 6 to 9, the threshold equal to the field. The skid buffer registers each accepted beat; the field and the CRC are registered the cycle after the beat that completes them. Icarus prints the same cycles. Data: nw_fpga.first_frame.