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1 Markets I: The Ecosystem and Exchange-Traded Marketsالأسواق عبر الإنترنت 2 Markets II: Rates, FX and Creditالأسواق عبر الإنترنت 3 Markets III: Commodities, Energy and Cryptoالأسواق عبر الإنترنت 4 Quantitative Methodsالأساليب عبر الإنترنت 5 Derivatives and Volatilityالمشتقات عبر الإنترنت 6 Rates, Credit, XVA and Riskالفائدة والائتمان والمخاطر عبر الإنترنت 7 Research Craft: Predictors, Backtests, Measurement, Portfoliosالبحث عبر الإنترنت 8 Strategies I: Equities and Futuresالاستراتيجيات عبر الإنترنت 9 Strategies II: Volatility, Relative Value, Macro and the Bank Desksالاستراتيجيات عبر الإنترنت 10 Microstructure and Executionالتنفيذ عبر الإنترنت 11 Market Making and High-Frequency Tradingصناعة السوق عبر الإنترنت 12 Machine Learning for Marketsتعلم الآلة عبر الإنترنت 13 Low-Latency Softwareالتكنولوجيا عبر الإنترنت 14 Networks, Hardware and Trading Infrastructureالتكنولوجيا عبر الإنترنت 15 Research, Data and Risk Platformsالتكنولوجيا عبر الإنترنت 16 The Desk and the Firmالشركة عبر الإنترنت 17 The Industry: Firms, Roles and Careersالمسارات المهنية عبر الإنترنت 18 The Interview Bookالمسارات المهنية عبر الإنترنت
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Quantitative Finance · المسرد

ما معنى Cache miss, working set؟

يُعرف أيضًا باسم: cache miss · working set

Definition 3.2 Low-Latency Software · الفصل 3 — Memory Hierarchy and Caches

A cache miss is an access to a line that is not in a given level, which must then be fetched from the next level down. The working set of a piece of code over an interval is the set of lines it touches in that interval; the level whose capacity it fits in sets its speed.

How an address selects its place in a set-associative cache. A 48 KiB, 12-way cache of 64-byte lines has 64 sets; bits 6 to 11 of the address choose the set, so addresses 4 KiB apart share a set.
Figure 3.1. How an address selects its place in a set-associative cache. A 48 KiB, 12-way cache of 64-byte lines has 64 sets; bits 6 to 11 of the address choose the set, so addresses 4 KiB apart share a set.
The memory staircase: time per dependent load through a buffer of one slot per cache line, against the buffer’s size. In address order the prefetcher hides almost all of it. Measured on a laptop (Intel Core Ultra 7 155H) under WSL2, no isolated cores, pinned to one CPU, the machine otherwise idle. Data: bench_mem.py.
Figure 3.2. The memory staircase: time per dependent load through a buffer of one slot per cache line, against the buffer’s size. In address order the prefetcher hides almost all of it. Measured on a laptop (Intel Core Ultra 7 155H) under WSL2, no isolated cores, pinned to one CPU, the machine otherwise idle. Data: bench_mem.py.

أمثلة

Example 3.3 (Geometry of a first-level cache)

A 48 KiB, 12-way cache with 64-byte lines has 48×1024/(64×12)=6448 \times 1024 / (64 \times 12) = 64 sets. The set index is bits 6 to 11; addresses that are equal modulo 64×64=4 09664 \times 64 = 4\,096 bytes fall into the same set. Thirteen hot structures placed at the same offset of thirteen 4 KiB pages cannot all stay in this cache, although together they occupy 832 bytes.

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