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Quantitative Finance · Glossaire

Qu'est-ce que « Cache miss, working set » ?

Aussi appelé : cache miss · working set

Definition 3.2 Low-Latency Software · Chapitre 3 — Memory Hierarchy and Caches

A cache miss is an access to a line that is not in a given level, which must then be fetched from the next level down. The working set of a piece of code over an interval is the set of lines it touches in that interval; the level whose capacity it fits in sets its speed.

How an address selects its place in a set-associative cache. A 48 KiB, 12-way cache of 64-byte lines has 64 sets; bits 6 to 11 of the address choose the set, so addresses 4 KiB apart share a set.
Figure 3.1. How an address selects its place in a set-associative cache. A 48 KiB, 12-way cache of 64-byte lines has 64 sets; bits 6 to 11 of the address choose the set, so addresses 4 KiB apart share a set.
The memory staircase: time per dependent load through a buffer of one slot per cache line, against the buffer’s size. In address order the prefetcher hides almost all of it. Measured on a laptop (Intel Core Ultra 7 155H) under WSL2, no isolated cores, pinned to one CPU, the machine otherwise idle. Data: bench_mem.py.
Figure 3.2. The memory staircase: time per dependent load through a buffer of one slot per cache line, against the buffer’s size. In address order the prefetcher hides almost all of it. Measured on a laptop (Intel Core Ultra 7 155H) under WSL2, no isolated cores, pinned to one CPU, the machine otherwise idle. Data: bench_mem.py.

Exemples

Example 3.3 (Geometry of a first-level cache)

A 48 KiB, 12-way cache with 64-byte lines has 48×1024/(64×12)=6448 \times 1024 / (64 \times 12) = 64 sets. The set index is bits 6 to 11; addresses that are equal modulo 64×64=4 09664 \times 64 = 4\,096 bytes fall into the same set. Thirteen hot structures placed at the same offset of thirteen 4 KiB pages cannot all stay in this cache, although together they occupy 832 bytes.

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