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Quantitative Finance · Begrippenlijst

Wat is Clock domain crossing?

Definition 6.7 Networks, Hardware and Trading Infrastructure · Hoofdstuk 6 — Programmable Hardware I: Architecture and Toolchain

A clock domain crossing is a signal passing between parts of a design clocked by unrelated clocks; it must go through a synchroniser or an asynchronous FIFO, or it will sometimes be sampled while it changes.

Model: a decision of 12 levels of logic split into registered stages (0.5\, n s per level, 0.4\, n s per register, model values). Left: the maximum clock, against the clocks two line rates require; right: the latency at that clock. Five stages are no better than four, because 12/5 = 12/4 = 3. Data: fig_fpga.py.
Figure 6.2. Model: a decision of 12 levels of logic split into registered stages (0.5 ns0.5\,\mathrm{n}\mathrm{s} per level, 0.4 ns0.4\,\mathrm{n}\mathrm{s} per register, model values). Left: the maximum clock, against the clocks two line rates require; right: the latency at that clock. Five stages are no better than four, because ⌈12/5⌉=⌈12/4⌉=3\lceil 12/5\rceil = \lceil 12/4\rceil = 3. Data: fig_fpga.py.
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